1. Field of the Invention
The invention relates in general to microprocessor systems and more particularly, to a system and method of optimizing performance of writecombining buffers in a shared buffer array.
2. Description of Related Art
The use of a cache memory with a processor facilitates the reduction of memory access time. The fundamental idea of cache organization is that by keeping the most frequently accessed instructions and data in the fast cache memory, the average memory access time will approach the access time of the cache. To achieve the maximum possible speed of operation, typical processors implement a cache hierarchy, that is, different levels of cache memory. The different levels of cache correspond to different distances from the processor core. The closer the cache is to the processor, the faster the data access. However, the faster the data access, the more costly it is to store data. As a result, the closer the cache level, the faster and smaller the cache.
The performance of cache memory is frequently measured in terms of its hit ratio. When the processor refers to memory and finds the word in cache, it is said to produce a hit. If the word is not found in cache, then it is in main memory and it counts as a miss. If a miss occurs, then an allocation is made at the entry indexed by the access. The access can be for loading data to the processor or storing data from the processor to memory. The cached information is retained by the cache memory until it is no longer needed, made invalid or replaced by other data, in which instances the cache entry is de-allocated.
The processor allows certain areas of system memory to be cached in the L1 and L2 caches. Other areas, such as memory mapped I/O, are uncacheable. Within individual regions of system memory, it also allows the memory type to be specified using a variety of system flags and registers. Write combining is an architectural extension to the cache protocol that can be used with writes of any memory type except strongly ordered uncacheable writes. The write combining technique combines several writes to the same cache line. Write combining requests to the bus controller are delayed until the line is fully written or an eviction condition occurs; therefore, reducing memory accesses and improving bus bandwidth.
However, the use of current write combining techniques suffer from a number of drawbacks. When there are a number of concurrent operations, it is difficult to manage the use of the write combining buffers. Each operation may have a different effect on the use of the write combining buffers, which might result in a degradation of the overall system performance. Also, using a shared buffer structure to support both write combining and non-write combining operations requires an algorithm to maximize performance out of a limited number of buffers.